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authorPeter Maydell <peter.maydell@linaro.org>2019-06-11 16:39:50 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-06-13 15:14:05 +0100
commitb8474540cbce4e2fa45010416375d1bcbe86dc15 (patch)
tree2a18f49e16e5f60fa9cb68c4f9d83ac199ec3a88 /target/arm
parent1882651afdb0ca44f0631192fbe65a71c660d809 (diff)
downloadqemu-b8474540cbce4e2fa45010416375d1bcbe86dc15.zip
target/arm: Convert VSQRT to decodetree
Convert the VSQRT instruction to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm')
-rw-r--r--target/arm/translate-vfp.inc.c20
-rw-r--r--target/arm/translate.c14
-rw-r--r--target/arm/vfp.decode5
3 files changed, 26 insertions, 13 deletions
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 6e06b2a130..ae2f77a873 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1908,3 +1908,23 @@ static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a)
{
return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm);
}
+
+static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
+{
+ gen_helper_vfp_sqrts(vd, vm, cpu_env);
+}
+
+static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a)
+{
+ return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm);
+}
+
+static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
+{
+ gen_helper_vfp_sqrtd(vd, vm, cpu_env);
+}
+
+static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a)
+{
+ return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index bb2282da92..64ebfedcea 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1390,14 +1390,6 @@ static inline void gen_vfp_neg(int dp)
gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
}
-static inline void gen_vfp_sqrt(int dp)
-{
- if (dp)
- gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
- else
- gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
-}
-
static inline void gen_vfp_cmp(int dp)
{
if (dp)
@@ -3098,7 +3090,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
return 1;
case 15:
switch (rn) {
- case 1 ... 2:
+ case 1 ... 3:
/* Already handled by decodetree */
return 1;
default:
@@ -3112,7 +3104,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
/* rn is opcode, encoded as per VFP_SREG_N. */
switch (rn) {
case 0x00: /* vmov */
- case 0x03: /* vsqrt */
break;
case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */
@@ -3290,9 +3281,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
case 0: /* cpy */
/* no-op */
break;
- case 3: /* sqrt */
- gen_vfp_sqrt(dp);
- break;
case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */
{
TCGv_ptr fpst = get_fpstatus_ptr(false);
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 79e41963be..2780e1ed9e 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -166,3 +166,8 @@ VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \
vd=%vd_sp vm=%vm_sp
VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \
vd=%vd_dp vm=%vm_dp
+
+VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \
+ vd=%vd_sp vm=%vm_sp
+VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \
+ vd=%vd_dp vm=%vm_dp