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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-24 07:50:19 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-10-24 07:51:37 +0100 |
| commit | f3cd8218d1d3e534877ce3f3cb61c6757d10f9df (patch) | |
| tree | 265d63a5818f20ab1182092d59b5f35f5110b1a9 /target/arm/translate.h | |
| parent | 41f6c113c9ebf475554b2546c3e4c175db02c569 (diff) | |
| download | qemu-f3cd8218d1d3e534877ce3f3cb61c6757d10f9df.zip | |
target/arm: Use gvec for VSRI, VSLI
Move shi_op and sli_op expanders from translate-a64.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011205206.3552-15-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
| -rw-r--r-- | target/arm/translate.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h index 5e13571b36..7eb759d041 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -198,6 +198,8 @@ extern const GVecGen3 bit_op; extern const GVecGen3 bif_op; extern const GVecGen2i ssra_op[4]; extern const GVecGen2i usra_op[4]; +extern const GVecGen2i sri_op[4]; +extern const GVecGen2i sli_op[4]; /* * Forward to the isar_feature_* tests given a DisasContext pointer. |