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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-05-22 15:55:12 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-05 17:23:09 +0100 |
| commit | d3c8c736f8b4bdd02831076286b1788232f46ced (patch) | |
| tree | a7be75406d0c464e683823bdbb7241340e02e13c /target/arm/translate.c | |
| parent | d02ded087030d2b5b5906b127d616acb2a6d1483 (diff) | |
| download | qemu-d3c8c736f8b4bdd02831076286b1788232f46ced.zip | |
target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift
group to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-2-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate.c')
| -rw-r--r-- | target/arm/translate.c | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index c61180ea61..41fef49dbe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5294,6 +5294,14 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if ((insn & 0x00380080) != 0) { /* Two registers and shift. */ op = (insn >> 8) & 0xf; + + switch (op) { + case 5: /* VSHL, VSLI */ + return 1; /* handled by decodetree */ + default: + break; + } + if (insn & (1 << 7)) { /* 64-bit shift. */ if (op > 7) { @@ -5387,16 +5395,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) gen_gvec_sri(size, rd_ofs, rm_ofs, shift, vec_size, vec_size); return 0; - - case 5: /* VSHL, VSLI */ - if (u) { /* VSLI */ - gen_gvec_sli(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { /* VSHL */ - tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; } if (size == 3) { |