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authorPortia Stephens <portia.stephens@xilinx.com>2017-09-07 13:54:55 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-09-07 13:54:55 +0100
commitc99a55d38dd5b5131f3fcbbaf41828a09ee62544 (patch)
tree711e7b4e65f11d6fe52f511ac078326f2ede67b2 /target/arm/translate.c
parentc79c0a314c43b78f6326d5f137bdbafdbf8e9766 (diff)
downloadqemu-c99a55d38dd5b5131f3fcbbaf41828a09ee62544.zip
target/arm: Add Jazelle feature
This adds a feature bit indicating support of the (trivial) Jazelle implementation if ARM_FEATURE_V6 is set or if the processor is arm926 or arm1026. This fixes the issue that any BXJ instruction will result in an illegal_op. BXJ instructions will now check if the architecture supports ARM_FEATURE_JAZELLE. Signed-off-by: Portia Stephens <portia.stephens@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com [PMM: edited commit message and comment text a bit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.c')
-rw-r--r--target/arm/translate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e7966e20ac..57899fa55b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -41,7 +41,7 @@
#define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
/* currently all emulated v5 cores are also v5TE, so don't bother */
#define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
-#define ENABLE_ARCH_5J 0
+#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE)
#define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
#define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
#define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)