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| author | Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 2021-01-12 12:45:00 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-01-19 14:38:51 +0000 |
| commit | b6ad6062f1e55bd5b9407ce89e55e3a08b83827c (patch) | |
| tree | d15eeb1e9e455c1cf82c80cde7e62267237b5a9a /target/arm/translate-a64.c | |
| parent | 6c85f906261226e87211506bd9f787fd48a09f17 (diff) | |
| download | qemu-b6ad6062f1e55bd5b9407ce89e55e3a08b83827c.zip | |
target/arm: add MMU stage 1 for Secure EL2
This adds the MMU indices for EL2 stage 1 in secure state.
To keep code contained, which is largelly identical between secure and
non-secure modes, the MMU indices are reassigned. The new assignments
provide a systematic pattern with a non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-8-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ef63edfc68..ffc060e5d7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -118,6 +118,10 @@ static int get_a64_user_mem_index(DisasContext *s) case ARMMMUIdx_SE10_1_PAN: useridx = ARMMMUIdx_SE10_0; break; + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + useridx = ARMMMUIdx_SE20_0; + break; default: g_assert_not_reached(); } |