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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-01 14:55:45 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-01 14:55:45 +0000 |
| commit | 4977986ca38fb1d5357532e1a8032b984047a369 (patch) | |
| tree | 54ea22a5274161b019bf60318376a065804017a2 /target/arm/translate-a64.c | |
| parent | c1e20801f5ee53472dbf2757df605543f3f4ce0b (diff) | |
| download | qemu-4977986ca38fb1d5357532e1a8032b984047a369.zip | |
target/arm/translate-a64: Don't underdecode SDOT and UDOT
In the AdvSIMD scalar x indexed element and vector x indexed element
encoding group, the SDOT and UDOT instructions are vector only,
and their opcode is unallocated in the scalar group. Correctly
UNDEF this unallocated encoding.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20190125182626.9221-8-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6c4b20daf2..07fa052393 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12641,7 +12641,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) break; case 0x0e: /* SDOT */ case 0x1e: /* UDOT */ - if (size != MO_32 || !dc_isar_feature(aa64_dp, s)) { + if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) { unallocated_encoding(s); return; } |