summaryrefslogtreecommitdiff
path: root/target/arm/translate-a64.c
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2019-01-21 10:23:12 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-01-21 10:38:54 +0000
commit476a4692f06e381117fb7ad0d04d37c9c2612198 (patch)
treead1e04698d9f052f6f70f7caf62aa5dd0351f6a0 /target/arm/translate-a64.c
parentba97be9f4a4ecaf16a1454dc669e5f3d935d3b63 (diff)
downloadqemu-476a4692f06e381117fb7ad0d04d37c9c2612198.zip
target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
We will shortly want to talk about TBI as it relates to data. Passing around a pair of variables is less convenient than a single variable. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
-rw-r--r--target/arm/translate-a64.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8d8f0a60b3..f49fe1de3a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -276,13 +276,15 @@ void gen_a64_set_pc_im(uint64_t val)
*/
static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
{
+ /* Note that TBII is TBI1:TBI0. */
+ int tbi = s->tbii;
if (s->current_el <= 1) {
/* Test if NEITHER or BOTH TBI values are set. If so, no need to
* examine bit 55 of address, can just generate code.
* If mixed, then test via generated code
*/
- if (s->tbi0 && s->tbi1) {
+ if (tbi == 3) {
TCGv_i64 tmp_reg = tcg_temp_new_i64();
/* Both bits set, sign extension from bit 55 into [63:56] will
* cover both cases
@@ -290,7 +292,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
tcg_gen_shli_i64(tmp_reg, src, 8);
tcg_gen_sari_i64(cpu_pc, tmp_reg, 8);
tcg_temp_free_i64(tmp_reg);
- } else if (!s->tbi0 && !s->tbi1) {
+ } else if (tbi == 0) {
/* Neither bit set, just load it as-is */
tcg_gen_mov_i64(cpu_pc, src);
} else {
@@ -300,7 +302,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55));
- if (s->tbi0) {
+ if (tbi == 1) {
/* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
tcg_gen_andi_i64(tcg_tmpval, src,
0x00FFFFFFFFFFFFFFull);
@@ -318,7 +320,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
tcg_temp_free_i64(tcg_tmpval);
}
} else { /* EL > 1 */
- if (s->tbi0) {
+ if (tbi != 0) {
/* Force tag byte to all zero */
tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull);
} else {
@@ -13807,8 +13809,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->condexec_cond = 0;
core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx);
- dc->tbi0 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI0);
- dc->tbi1 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI1);
+ dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII);
dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
#if !defined(CONFIG_USER_ONLY)
dc->user = (dc->current_el == 0);