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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-04-02 15:12:58 +0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-05-10 11:12:50 -0700 |
| commit | 7350d553b5066abdc662045d7db5cdb73d0f9d53 (patch) | |
| tree | d0bd112eb3cb2b9e0ec012d3b54b3b15430a70a5 /target/arm/internals.h | |
| parent | e41c94529740cc26ac6d6eea4bb8b6f77466f5e4 (diff) | |
| download | qemu-7350d553b5066abdc662045d7db5cdb73d0f9d53.zip | |
target/arm: Convert to CPUClass::tlb_fill
Cc: qemu-arm@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
| -rw-r--r-- | target/arm/internals.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..5a02f458f3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -761,10 +761,12 @@ static inline bool arm_extabort_type(MemTxResult result) return result != MEMTX_DECODE_ERROR; } -/* Do a page table walk and add page to TLB if possible */ -bool arm_tlb_fill(CPUState *cpu, vaddr address, - MMUAccessType access_type, int mmu_idx, - ARMMMUFaultInfo *fi); +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN; /* Return true if the stage 1 translation regime is using LPAE format page * tables */ |