diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-03-31 15:34:07 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-04-03 19:24:20 +0100 |
| commit | 07d1be3b3aac20c21ac4a95c7f3f01a3622a31a3 (patch) | |
| tree | 22afeadb73378f96c967f9ae5d9ffa9b3132cdda /target/arm/helper.c | |
| parent | f4e1dbc578a051db08a40c05276ebf525b98f949 (diff) | |
| download | qemu-07d1be3b3aac20c21ac4a95c7f3f01a3622a31a3.zip | |
target/arm: Remove obsolete TODO note from get_phys_addr_lpae()
An old comment in get_phys_addr_lpae() claims that the code does not
support the different format TCR for VTCR_EL2. This used to be true
but it is not true now (in particular the aa64_va_parameters() and
aa32_va_parameters() functions correctly handle the different
register format by checking whether the mmu_idx is Stage2).
Remove the out of date parts of the comment.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200331143407.3186-1-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index ed7eb8ab54..7e9ea5d20f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10753,12 +10753,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; - /* TODO: - * This code does not handle the different format TCR for VTCR_EL2. - * This code also does not support shareability levels. - * Attribute and permission bit handling should also be checked when adding - * support for those page table walks. - */ + /* TODO: This code does not support shareability levels. */ if (aarch64) { param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); |