summaryrefslogtreecommitdiff
path: root/target-sparc
diff options
context:
space:
mode:
authorIgor V. Kovalenko <igor.v.kovalenko@gmail.com>2010-01-07 23:28:21 +0300
committerBlue Swirl <blauwirbel@gmail.com>2010-01-08 17:15:45 +0000
commit709f2c1b23ceb88c78a116e9a9c22e2a4837f62a (patch)
tree2853a78cd9fb5fc48a3582d800c185b1c49bbf72 /target-sparc
parent4dc28134f3d7db0033c6b3c5bc4be9a91adb3e2b (diff)
downloadqemu-709f2c1b23ceb88c78a116e9a9c22e2a4837f62a.zip
sparc64: add macros to deal with softint and timer interrupt
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/cpu.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 1fe4d0f1e4..0f0e38cf2c 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -394,6 +394,8 @@ typedef struct CPUSPARCState {
uint64_t fprs;
uint64_t tick_cmpr, stick_cmpr;
void *tick, *stick;
+#define TICK_NPT_MASK 0x8000000000000000ULL
+#define TICK_INT_DIS 0x8000000000000000ULL
uint64_t gsr;
uint32_t gl; // UA2005
/* UA 2005 hyperprivileged registers */
@@ -402,6 +404,8 @@ typedef struct CPUSPARCState {
uint32_t softint;
#define SOFTINT_TIMER 1
#define SOFTINT_STIMER (1 << 16)
+#define SOFTINT_INTRMASK (0xFFFE)
+#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
#endif
sparc_def_t *def;
} CPUSPARCState;