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| author | Richard Henderson <rth@twiddle.net> | 2012-09-05 17:32:54 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-01-05 12:18:44 -0800 |
| commit | 1c2687518235aa38dd3dd270fc216e559d0509eb (patch) | |
| tree | f2dac1233c55a916693921e873cdd3b24fc854f5 /target-s390x/translate.c | |
| parent | 403e217f4073b885b7e02a1b64054ceca7202bf6 (diff) | |
| download | qemu-1c2687518235aa38dd3dd270fc216e559d0509eb.zip | |
target-s390: Implement COMPARE AND TRAP
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-s390x/translate.c')
| -rw-r--r-- | target-s390x/translate.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/target-s390x/translate.c b/target-s390x/translate.c index dbc43a6754..e94c663180 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1705,6 +1705,35 @@ static ExitStatus op_cvd(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_ct(DisasContext *s, DisasOps *o) +{ + int m3 = get_field(s->fields, m3); + int lab = gen_new_label(); + TCGv_i32 t; + TCGCond c; + + /* Bit 3 of the m3 field is reserved and should be zero. + Choose to ignore it wrt the ltgt_cond table above. */ + c = tcg_invert_cond(ltgt_cond[m3 & 14]); + if (s->insn->data) { + c = tcg_unsigned_cond(c); + } + tcg_gen_brcond_i64(c, o->in1, o->in2, lab); + + /* Set DXC to 0xff. */ + t = tcg_temp_new_i32(); + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUS390XState, fpc)); + tcg_gen_ori_i32(t, t, 0xff00); + tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, fpc)); + tcg_temp_free_i32(t); + + /* Trap. */ + gen_program_exception(s, PGM_DATA); + + gen_set_label(lab); + return NO_EXIT; +} + #ifndef CONFIG_USER_ONLY static ExitStatus op_diag(DisasContext *s, DisasOps *o) { |