diff options
| author | Tom Musta <tommusta@gmail.com> | 2014-02-10 11:26:56 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:06:49 +0100 |
| commit | 38a853375e63ea7315e138d7016ed387d744e43d (patch) | |
| tree | 6244bfa4a24647aaa3b6563b15bbd800b13e0972 /target-ppc | |
| parent | 52a4984d97a942f35debb1887cb53d7f09bf1e26 (diff) | |
| download | qemu-38a853375e63ea7315e138d7016ed387d744e43d.zip | |
target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions
This patch adds a flag to identify the load/store quadword instructions
that are introduced with Power ISA 2.07.
The flag is added to the Power8 model since P8 supports these
instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 4 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 3 |
2 files changed, 5 insertions, 2 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index d02fd0425e..365627b3b1 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1890,12 +1890,14 @@ enum { PPC2_FP_TST_ISA206 = 0x0000000000000800ULL, /* ISA 2.07 bctar instruction */ PPC2_BCTAR_ISA207 = 0x0000000000001000ULL, + /* ISA 2.07 load/store quadword */ + PPC2_LSQ_ISA207 = 0x0000000000002000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_BCTAR_ISA207) + PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index cb84a8f987..64f56de9ce 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7171,7 +7171,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207; + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207; pcc->msr_mask = 0x800000000284FF36ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) |