diff options
| author | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2010-01-11 15:32:47 +0100 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2010-01-14 14:42:30 +0100 |
| commit | dcbc9a70af47fdd49d053f6a544a86de8dca398a (patch) | |
| tree | f588dbbf3d7a3b78e4a80d18e329d5a428c2e385 /target-ppc/helper.c | |
| parent | ec5c3e487eb49100e6cb1b84e7f0bd022fbbf54b (diff) | |
| download | qemu-dcbc9a70af47fdd49d053f6a544a86de8dca398a.zip | |
ppc-40x: Correct ESR for zone protection faults.
Raise the zone protection fault in ESR for TLB faults caused by
zone protection bits.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'target-ppc/helper.c')
| -rw-r--r-- | target-ppc/helper.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/target-ppc/helper.c b/target-ppc/helper.c index f9b55890d3..a4fae31e38 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -1171,6 +1171,8 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, break; case 0x0: if (pr != 0) { + /* Raise Zone protection fault. */ + env->spr[SPR_40x_ESR] = 1 << 22; ctx->prot = 0; ret = -2; break; @@ -1183,6 +1185,8 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, ctx->prot = tlb->prot; ctx->prot |= PAGE_EXEC; ret = check_prot(ctx->prot, rw, access_type); + if (ret == -2) + env->spr[SPR_40x_ESR] = 0; break; } if (ret >= 0) { @@ -1580,11 +1584,20 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, /* Access rights violation */ env->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; - env->spr[SPR_DAR] = address; - if (rw == 1) - env->spr[SPR_DSISR] = 0x0A000000; - else - env->spr[SPR_DSISR] = 0x08000000; + if (env->mmu_model == POWERPC_MMU_SOFT_4xx + || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) { + env->spr[SPR_40x_DEAR] = address; + if (rw) { + env->spr[SPR_40x_ESR] |= 0x00800000; + } + } else { + env->spr[SPR_DAR] = address; + if (rw == 1) { + env->spr[SPR_DSISR] = 0x0A000000; + } else { + env->spr[SPR_DSISR] = 0x08000000; + } + } break; case -4: /* Direct store exception */ |