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| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-07-04 22:17:05 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-07-04 22:17:05 +0000 |
| commit | fdabc366bd922d3029b42864ecf268103d8ca8e6 (patch) | |
| tree | ba6acc1a6da59ed101291af14d15a1c09e78f1de /target-ppc/cpu.h | |
| parent | 2157fa0682e3b2a1cb0b4864e6f4b86f88b1fae2 (diff) | |
| download | qemu-fdabc366bd922d3029b42864ecf268103d8ca8e6.zip | |
correct split between helper.c and op_helper.c - moved some uops to op_helper.c (Jocelyn Mayer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1504 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7fc79434a1..8dd9cc12dd 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -32,6 +32,15 @@ #define TARGET_HAS_ICE 1 +/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC + * have different cache line sizes + */ +#define ICACHE_LINE_SIZE 32 +#define DCACHE_LINE_SIZE 32 + +/* XXX: put this in a common place */ +#define likely(x) __builtin_expect(!!(x), 1) + /*****************************************************************************/ /* PVR definitions for most known PowerPC */ enum { |