diff options
| author | Anthony Liguori <aliguori@us.ibm.com> | 2011-05-12 08:08:12 -0500 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2011-05-12 08:08:12 -0500 |
| commit | 711c21280b2cb56060859cc574221a8bf40f908a (patch) | |
| tree | 9f5385c53ac50e613ae34d4165d02460ef993f0f /target-mips | |
| parent | 89bb563f6912b3f538d6bdf5833881ed7cdbd923 (diff) | |
| parent | 2f172849b63b166fe876aa97b411f63ee7d17467 (diff) | |
| download | qemu-711c21280b2cb56060859cc574221a8bf40f908a.zip | |
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
Conflicts:
cpu-all.h
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 590e092a1d..d55c522bf3 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -38,7 +38,7 @@ ((1 << CP0C2_M)) /* No config4, no DSP ASE, no large physaddr (PABITS), - no external interrupt controller, no vectored interupts, + no external interrupt controller, no vectored interrupts, no 1kb pages, no SmartMIPS ASE, no trace logic */ #define MIPS_CONFIG3 \ ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ @@ -477,7 +477,7 @@ static const mips_def_t mips_defs[] = .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), .SYNCI_Step = 16, .CCRes = 2, - .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writeable*/ + .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), .SEGBITS = 40, .PABITS = 40, |