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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-12 21:01:26 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-12 21:01:26 +0000 |
| commit | d0dc7dc3274a88db1c9941614454ed842d62cf91 (patch) | |
| tree | 46e369f2d52daecef62ef93665fdc6dbb21c3b82 /target-mips/cpu.h | |
| parent | 577d8dd43779f6ae75cb1b49606443ddab870bda (diff) | |
| download | qemu-d0dc7dc3274a88db1c9941614454ed842d62cf91.zip | |
Make MIPS MT implementation more cache friendly.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3981 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 8b6b8bdb0e..4e0a09d761 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -142,7 +142,7 @@ typedef struct mips_def_t mips_def_t; typedef struct CPUMIPSState CPUMIPSState; struct CPUMIPSState { /* General integer registers */ - target_ulong gpr[32][MIPS_SHADOW_SET_MAX]; + target_ulong gpr[MIPS_SHADOW_SET_MAX][32]; /* Special registers */ target_ulong PC[MIPS_TC_MAX]; #if TARGET_LONG_BITS > HOST_LONG_BITS @@ -150,9 +150,9 @@ struct CPUMIPSState { target_ulong t1; target_ulong t2; #endif - target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX]; - target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX]; - target_ulong ACX[MIPS_DSP_ACC][MIPS_TC_MAX]; + target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC]; + target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC]; + target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC]; target_ulong DSPControl[MIPS_TC_MAX]; CPUMIPSMVPContext *mvp; |