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| author | Leon Alrae <leon.alrae@imgtec.com> | 2014-07-07 11:23:59 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-03 11:48:34 +0000 |
| commit | 7207c7f9d74816c32783a394d8072d1f978157ac (patch) | |
| tree | 05c22755fc89eceee9d23533de96bc06d9abdd97 /target-mips/cpu.h | |
| parent | 2fb58b73746e2f99ac85e82160277b18b18279be (diff) | |
| download | qemu-7207c7f9d74816c32783a394d8072d1f978157ac.zip | |
target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}
PageGrain needs rw bitmask which differs between MIPS architectures.
In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable,
whereas in R6 they are read-only 1.
On MIPS64 mtc0 instruction left shifts bits 31:30 for MIPS32 backward
compatiblity, therefore there are separate mtc0 and dmtc0 helpers.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 13f3a48198..38f90f27f4 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -243,7 +243,10 @@ struct CPUMIPSState { target_ulong CP0_Context; target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; int32_t CP0_PageMask; + int32_t CP0_PageGrain_rw_bitmask; int32_t CP0_PageGrain; +#define CP0PG_RIE 31 +#define CP0PG_XIE 30 int32_t CP0_Wired; int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; @@ -377,6 +380,7 @@ struct CPUMIPSState { #define CP0C3_M 31 #define CP0C3_ISA_ON_EXC 16 #define CP0C3_ULRI 13 +#define CP0C3_RXI 12 #define CP0C3_DSPP 10 #define CP0C3_LPA 7 #define CP0C3_VEIC 6 |