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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-28 20:36:48 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-28 20:36:48 +0000 |
| commit | 6e473128b61901441fa2889dfa2079881895a9f9 (patch) | |
| tree | f6be8334ee0b7031f5c5dcb45c4024b6d9c3a4b8 /target-mips/cpu.h | |
| parent | 85aa199ad7755880060d0481dc1c762c372a1799 (diff) | |
| download | qemu-6e473128b61901441fa2889dfa2079881895a9f9.zip | |
Handle PX/UX status flags correctly, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2892 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 9cddc174d2..17ac4ac875 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -260,6 +260,7 @@ struct CPUMIPSState { #define MIPS_HFLAG_UM 0x0001 /* user mode */ #define MIPS_HFLAG_DM 0x0008 /* Debug mode */ #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */ +#define MIPS_HFLAG_64 0x0020 /* 64-bit instructions enabled */ #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */ /* If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can |