diff options
author | Andreas Färber <afaerber@suse.de> | 2013-08-25 18:53:55 +0200 |
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committer | Andreas Färber <afaerber@suse.de> | 2014-03-13 19:01:49 +0100 |
commit | 8c2e1b0093aa4a89548df47d969217d8b0dfd070 (patch) | |
tree | 16656127c1a0c6194b25f29bd54f612b9c1f8679 /target-mips/cpu.c | |
parent | 1cf5ccbca8915277098727d900d52c495a711f88 (diff) | |
download | qemu-8c2e1b0093aa4a89548df47d969217d8b0dfd070.zip |
cpu: Turn cpu_has_work() into a CPUClass hook
Default to false.
Tidy variable naming and inline cast uses while at it.
Tested-by: Jia Liu <proljc@gmail.com> (or32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-mips/cpu.c')
-rw-r--r-- | target-mips/cpu.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 9dd47e84f7..0a2dc46144 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -45,6 +45,35 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) env->hflags |= tb->flags & MIPS_HFLAG_BMASK; } +static bool mips_cpu_has_work(CPUState *cs) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + bool has_work = false; + + /* It is implementation dependent if non-enabled interrupts + wake-up the CPU, however most of the implementations only + check for interrupts that can be taken. */ + if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + cpu_mips_hw_interrupts_pending(env)) { + has_work = true; + } + + /* MIPS-MT has the ability to halt the CPU. */ + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + /* The QEMU model will issue an _WAKE request whenever the CPUs + should be woken up. */ + if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + has_work = true; + } + + if (!mips_vpe_active(env)) { + has_work = false; + } + } + return has_work; +} + /* CPUClass::reset() */ static void mips_cpu_reset(CPUState *s) { @@ -97,6 +126,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) mcc->parent_reset = cc->reset; cc->reset = mips_cpu_reset; + cc->has_work = mips_cpu_has_work; cc->do_interrupt = mips_cpu_do_interrupt; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; |