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| author | Andreas Färber <afaerber@suse.de> | 2013-01-16 03:48:37 +0100 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-02-16 14:50:57 +0100 |
| commit | c1caf1d961288e41c25de6631c6751ae7baa20f0 (patch) | |
| tree | 282ab0ab9836b6b8abf8bd4db576be18159dc93d /target-mips/cpu-qom.h | |
| parent | 746b03b27cac48be5a376d8635ffaf568339ebd7 (diff) | |
| download | qemu-c1caf1d961288e41c25de6631c6751ae7baa20f0.zip | |
target-mips: Introduce QOM realizefn for MIPSCPU
Introduce a realizefn and set realized = true from cpu_mips_init().
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-mips/cpu-qom.h')
| -rw-r--r-- | target-mips/cpu-qom.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h index 2a4b812402..55aa692a85 100644 --- a/target-mips/cpu-qom.h +++ b/target-mips/cpu-qom.h @@ -37,6 +37,7 @@ /** * MIPSCPUClass: + * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * * A MIPS CPU model. @@ -46,6 +47,7 @@ typedef struct MIPSCPUClass { CPUClass parent_class; /*< public >*/ + DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } MIPSCPUClass; |