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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-11 20:58:36 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-11 20:58:36 +0000 |
| commit | 2681b45add5f22694d645183a82824722b7191be (patch) | |
| tree | 1a5774d5aa152b3bc20901fe4cd0ea8558914bea /target-mips/TODO | |
| parent | 5d0fc900d35e9f272c79d199e5854be8301dccf3 (diff) | |
| download | qemu-2681b45add5f22694d645183a82824722b7191be.zip | |
Update TODO list.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4735 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/TODO')
| -rw-r--r-- | target-mips/TODO | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-mips/TODO b/target-mips/TODO index c58956cff6..6722c20d7a 100644 --- a/target-mips/TODO +++ b/target-mips/TODO @@ -30,6 +30,11 @@ General each ASID change. Using the MMU modes to implement ASIDs hinges on implementing the global bit efficiently. - save/restore of the CPU state is not implemented (see machine.c). +- Improve cpu state handling: + Step 1) Collect all the TC state in a single struct, so we need only + a single global pointer per TC. + Step 2) Use only a single TC context as working context, and copy the + contexts on TC switch. Likewise for FPU contexts. MIPS64 ------ |