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author | Yang Zhang <yang.z.zhang@intel.com> | 2012-08-02 18:04:09 +0200 |
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committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-09-10 13:52:28 -0500 |
commit | 56038ef6234e5fb3d01bad1f6df37c2ccab82af9 (patch) | |
tree | 4b1cfa3e8ed843e5b6b9cd99251355f0f6a78627 /target-lm32/helper.c | |
parent | 0281518a1c7dd3577dea9ccc78869ecff954589c (diff) | |
download | qemu-56038ef6234e5fb3d01bad1f6df37c2ccab82af9.zip |
RTC: Update the RTC clock only when reading it
Calculate guest RTC based on the time of the last update, instead of
using timers. The formula is
(base_rtc + guest_time_now - guest_time_last_update + offset)
Base_rtc is the RTC value when the RTC was last updated.
Guest_time_now is the guest time when the access happens.
Guest_time_last_update was the guest time when the RTC was last updated.
Offset is used when divider reset happens or the set bit is toggled.
The timer is kept in order to signal interrupts, but it only needs to
run when either UF or AF is cleared. When the bits are both set, the
timer does not run.
UIP is now synthesized when reading register A. If the timer is not set,
or if there is more than one second before it (as is the case at the
end of this series), the leading edge of UIP is computed and the rising
edge occurs 220us later. If the update timer occurs within one second,
however, the rising edge of the AF and UF bits should coincide withe
the falling edge of UIP. We do not know exactly when this will happen
because there could be delays in the servicing of the timer. Hence, in
this case reading register A only computes for the rising edge of UIP,
and latches the bit until the timer is fired and clears it.
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'target-lm32/helper.c')
0 files changed, 0 insertions, 0 deletions