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authorRichard Henderson <rth@twiddle.net>2013-11-02 08:28:40 -1000
committerRichard Henderson <rth@twiddle.net>2014-01-07 11:36:31 -0800
commitc8fbc479674d00a8f9dd63f9a9d4978c4c4b96d9 (patch)
tree6f1808f3c4b528ca877ff2a9e32a80384ccd305e /target-i386/translate.c
parentee3138da2f76b415cbce6466aa4083a84fc26241 (diff)
downloadqemu-c8fbc479674d00a8f9dd63f9a9d4978c4c4b96d9.zip
target-i386: Tidy mov[sz][bw]
We can use the MO_SIGN bit to tidy the reg-reg switch statement as well as pass it on to gen_op_ld_v, eliminating one call. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386/translate.c')
-rw-r--r--target-i386/translate.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9205b72da0..f3baa4d118 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -5618,11 +5618,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1be: /* movsbS Gv, Eb */
case 0x1bf: /* movswS Gv, Eb */
{
- int d_ot;
+ TCGMemOp d_ot;
+ TCGMemOp s_ot;
+
/* d_ot is the size of destination */
d_ot = dflag + MO_16;
/* ot is the size of source */
ot = (b & 1) + MO_8;
+ /* s_ot is the sign+size of source */
+ s_ot = b & 8 ? MO_SIGN | ot : ot;
+
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5630,29 +5635,25 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3) {
gen_op_mov_TN_reg(ot, 0, rm);
- switch(ot | (b & 8)) {
- case MO_8:
+ switch (s_ot) {
+ case MO_UB:
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
break;
- case MO_8 | 8:
+ case MO_SB:
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
break;
- case MO_16:
+ case MO_UW:
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
break;
default:
- case MO_16 | 8:
+ case MO_SW:
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
break;
}
gen_op_mov_reg_T0(d_ot, reg);
} else {
gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
- if (b & 8) {
- gen_op_ld_v(s, ot | MO_SIGN, cpu_T[0], cpu_A0);
- } else {
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- }
+ gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(d_ot, reg);
}
}