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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2004-05-08 21:08:41 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2004-05-08 21:08:41 +0000
commit2ee73ac3a855fb0cfba3db91fdd1ecebdbc6f971 (patch)
tree9759c191fd2b12e00749c4ea4b45298c9336c35c /target-i386/helper.c
parent28c3ee3fed3bb51c45320bec1ede3585cd36f8a4 (diff)
downloadqemu-2ee73ac3a855fb0cfba3db91fdd1ecebdbc6f971.zip
division by zero FPU exception support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@795 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/helper.c')
-rw-r--r--target-i386/helper.c31
1 files changed, 29 insertions, 2 deletions
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 27a7a5559c..f2305e32c4 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -24,7 +24,7 @@
#if 0
#define raise_exception_err(a, b)\
do {\
- printf("raise_exception line=%d\n", __LINE__);\
+ fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
(raise_exception_err)(a, b);\
} while (0)
#endif
@@ -859,10 +859,11 @@ void do_interrupt(int intno, int is_int, int error_code,
if (loglevel & (CPU_LOG_PCALL | CPU_LOG_INT)) {
if ((env->cr[0] & CR0_PE_MASK)) {
static int count;
- fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:%08x SP=%04x:%08x",
+ fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:%08x pc=%08x SP=%04x:%08x",
count, intno, error_code, is_int,
env->hflags & HF_CPL_MASK,
env->segs[R_CS].selector, EIP,
+ (int)env->segs[R_CS].base + EIP,
env->segs[R_SS].selector, ESP);
if (intno == 0x0e) {
fprintf(logfile, " CR2=%08x", env->cr[2]);
@@ -1990,6 +1991,32 @@ void helper_fstt_ST0_A0(void)
helper_fstt(ST0, (uint8_t *)A0);
}
+void fpu_set_exception(int mask)
+{
+ env->fpus |= mask;
+ if (env->fpus & (~env->fpuc & FPUC_EM))
+ env->fpus |= FPUS_SE | FPUS_B;
+}
+
+CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
+{
+ if (b == 0.0)
+ fpu_set_exception(FPUS_ZE);
+ return a / b;
+}
+
+void fpu_raise_exception(void)
+{
+ if (env->cr[0] & CR0_NE_MASK) {
+ raise_exception(EXCP10_COPR);
+ }
+#if !defined(CONFIG_USER_ONLY)
+ else {
+ cpu_set_ferr(env);
+ }
+#endif
+}
+
/* BCD ops */
void helper_fbld_ST0_A0(void)