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authorChao Peng <chao.p.peng@linux.intel.com>2014-10-23 11:02:43 +0800
committerPaolo Bonzini <pbonzini@redhat.com>2014-10-24 18:03:14 +0200
commit9aecd6f8aef653cea58932f06a2740299dbe5fd3 (patch)
tree79a8542e34c0b378d4b2f8bcd64b5fc3c3a0a3d4 /target-i386/cpu.c
parentc6561586f0f858635ccda0bfa97046e4e82af276 (diff)
downloadqemu-9aecd6f8aef653cea58932f06a2740299dbe5fd3.zip
target-i386: add Intel AVX-512 support
Add AVX512 feature bits, register definition and corresponding xsave/vmstate support. Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target-i386/cpu.c')
-rw-r--r--target-i386/cpu.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 69a2bd39c5..e1946016ad 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -259,8 +259,8 @@ static const char *svm_feature_name[] = {
static const char *cpuid_7_0_ebx_feature_name[] = {
"fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
"bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
- NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
+ NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
};
static const char *cpuid_apm_edx_feature_name[] = {
@@ -426,6 +426,12 @@ static const ExtSaveArea ext_save_areas[] = {
.offset = 0x3c0, .size = 0x40 },
[4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
.offset = 0x400, .size = 0x40 },
+ [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
+ .offset = 0x440, .size = 0x40 },
+ [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
+ .offset = 0x480, .size = 0x200 },
+ [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
+ .offset = 0x680, .size = 0x400 },
};
const char *get_register_name_32(unsigned int reg)