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| author | Peter Maydell <peter.maydell@linaro.org> | 2011-03-15 16:26:52 +0000 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-04-01 22:33:47 +0200 |
| commit | e318a60b94b152c1e80125861a8917ae177d845e (patch) | |
| tree | a419e4ab49039d317ccffdbf5d8e423a9a1f9e69 /target-arm | |
| parent | 8e18cde30b06d2e7411bf38091c4e30602f85cdd (diff) | |
| download | qemu-e318a60b94b152c1e80125861a8917ae177d845e.zip | |
target-arm: Don't leak TCG temp for UNDEFs in Neon load/store space
Move the allocation and freeing of the TCG temp used for the address for
Neon load/store instructions so that we don't allocate the temporary
until we've done enough decoding to know that the instruction is not
an UNDEF pattern; this avoids leaking the TCG temp in these cases.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 1dfd4823f5..39512bc62f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3810,7 +3810,6 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) rn = (insn >> 16) & 0xf; rm = insn & 0xf; load = (insn & (1 << 21)) != 0; - addr = tcg_temp_new_i32(); if ((insn & (1 << 23)) == 0) { /* Load store all elements. */ op = (insn >> 8) & 0xf; @@ -3822,6 +3821,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) spacing = neon_ls_element_type[op].spacing; if (size == 3 && (interleave | spacing) != 1) return 1; + addr = tcg_temp_new_i32(); load_reg_var(s, addr, rn); stride = (1 << size) * interleave; for (reg = 0; reg < nregs; reg++) { @@ -3907,6 +3907,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) } rd += spacing; } + tcg_temp_free_i32(addr); stride = nregs * 8; } else { size = (insn >> 10) & 3; @@ -3932,6 +3933,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) if (nregs == 3 && a == 1) { return 1; } + addr = tcg_temp_new_i32(); load_reg_var(s, addr, rn); if (nregs == 1) { /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */ @@ -3955,6 +3957,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) rd += stride; } } + tcg_temp_free_i32(addr); stride = (1 << size) * nregs; } else { /* Single element. */ @@ -3976,6 +3979,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) abort(); } nregs = ((insn >> 8) & 3) + 1; + addr = tcg_temp_new_i32(); load_reg_var(s, addr, rn); for (reg = 0; reg < nregs; reg++) { if (load) { @@ -4017,10 +4021,10 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) rd += stride; tcg_gen_addi_i32(addr, addr, 1 << size); } + tcg_temp_free_i32(addr); stride = nregs * (1 << size); } } - tcg_temp_free_i32(addr); if (rm != 15) { TCGv base; |