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authorAnthony Liguori <aliguori@us.ibm.com>2013-06-28 11:48:09 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2013-06-28 11:48:09 -0500
commit8a9c98aedc1a3fb4dfbebeccc926e273df54f2ba (patch)
treeb800dd8b6131717bf397103ec4d7199f67ea0c5c /target-arm
parent36125631e79d53ffb9365740f43f386e2171d116 (diff)
parentc658b94f6e8c206c59d02aa6fbac285b86b53d2c (diff)
downloadqemu-8a9c98aedc1a3fb4dfbebeccc926e273df54f2ba.zip
Merge remote-tracking branch 'afaerber/qom-cpu' into staging
# By Andreas Färber # Via Andreas Färber * afaerber/qom-cpu: (24 commits) cpu: Turn cpu_unassigned_access() into a CPUState hook hwaddr: Make hwaddr type usable beyond softmmu cpu: Change qemu_init_vcpu() argument to CPUState cpus: Change qemu_dummy_start_vcpu() argument to CPUState cpus: Change qemu_kvm_start_vcpu() argument to CPUState cpus: Change cpu_handle_guest_debug() argument to CPUState gdbstub: Set gdb_set_stop_cpu() argument to CPUState kvm: Change kvm_cpu_exec() argument to CPUState kvm: Change kvm_handle_internal_error() argument to CPUState cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks cpus: Change qemu_kvm_init_cpu_signals() argument to CPUState kvm: Change kvm_set_signal_mask() argument to CPUState cpus: Change qemu_kvm_wait_io_event() argument to CPUState cpus: Change cpu_thread_is_idle() argument to CPUState cpu: Change cpu_exit() argument to CPUState kvm: Change cpu_synchronize_state() argument to CPUState kvm: Change kvm_cpu_synchronize_state() argument to CPUState gdbstub: Simplify find_cpu() cpu: Guard cpu_{save,load}() definitions target-openrisc: Register VMStateDescription for OpenRISCCPU ...
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/arm-semi.c3
-rw-r--r--target-arm/cpu-qom.h3
-rw-r--r--target-arm/cpu.c2
-rw-r--r--target-arm/translate.c6
4 files changed, 10 insertions, 4 deletions
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index f0637a43f2..5f01bca119 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -178,6 +178,7 @@ static void arm_semi_flen_cb(CPUARMState *env, target_ulong ret, target_ulong er
#define SET_ARG(n, val) put_user_ual(val, args + (n) * 4)
uint32_t do_arm_semihosting(CPUARMState *env)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
target_ulong args;
target_ulong arg0, arg1, arg2, arg3;
char * s;
@@ -549,7 +550,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
exit(0);
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
abort();
}
}
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 25239b8952..ef6261fd17 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -144,4 +144,7 @@ void init_cpreg_list(ARMCPU *cpu);
void arm_cpu_do_interrupt(CPUState *cpu);
void arm_v7m_cpu_do_interrupt(CPUState *cpu);
+void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+
#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2371f48057..1bc227e9a6 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -208,7 +208,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
init_cpreg_list(cpu);
cpu_reset(CPU(cpu));
- qemu_init_vcpu(env);
acc->parent_realize(dev, errp);
}
@@ -816,6 +815,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = arm_cpu_class_by_name;
cc->do_interrupt = arm_cpu_do_interrupt;
+ cc->dump_state = arm_cpu_dump_state;
cpu_class_set_vmsd(cc, &vmstate_arm_cpu);
}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 2a18ffe5cf..af2aef29e3 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -10085,9 +10085,11 @@ static const char *cpu_mode_names[16] = {
"???", "???", "???", "und", "???", "???", "???", "sys"
};
-void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
int i;
uint32_t psr;