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| author | Blue Swirl <blauwirbel@gmail.com> | 2012-09-04 20:08:34 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-09-15 17:44:32 +0000 |
| commit | 1ce94f81eca411b64c71a05b11e4c51dea86639f (patch) | |
| tree | 838ac8facb0502db401f2e47ebc31509b86da57b /target-arm/translate.c | |
| parent | 04a130eaa10f3d2af6ac9fb68a8daffd40a2f9aa (diff) | |
| download | qemu-1ce94f81eca411b64c71a05b11e4c51dea86639f.zip | |
target-arm: convert void helpers
Add an explicit CPUState parameter instead of relying on AREG0.
For easier review, convert only op helpers which don't return any value.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index edef79a2cf..6f651d93c7 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -199,7 +199,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) static inline void gen_set_cpsr(TCGv var, uint32_t mask) { TCGv tmp_mask = tcg_const_i32(mask); - gen_helper_cpsr_write(var, tmp_mask); + gen_helper_cpsr_write(cpu_env, var, tmp_mask); tcg_temp_free_i32(tmp_mask); } /* Set NZCV flags from the high 4 bits of var. */ @@ -209,7 +209,7 @@ static void gen_exception(int excp) { TCGv tmp = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, excp); - gen_helper_exception(tmp); + gen_helper_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); } @@ -7719,7 +7719,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = gen_ld32(addr, IS_USER(s)); if (user) { tmp2 = tcg_const_i32(i); - gen_helper_set_user_reg(tmp2, tmp); + gen_helper_set_user_reg(cpu_env, tmp2, tmp); tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp); } else if (i == rn) { @@ -9913,7 +9913,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env, /* nothing more to generate */ break; case DISAS_WFI: - gen_helper_wfi(); + gen_helper_wfi(cpu_env); break; case DISAS_SWI: gen_exception(EXCP_SWI); |