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| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2014-09-29 18:48:49 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-09-29 18:48:49 +0100 |
| commit | 9e729b57ac2a3adebee2746a2106a70eb8230a72 (patch) | |
| tree | 40c42b07039d287afba28b9fab38d784f69344fe /target-arm/cpu.h | |
| parent | 64e0e2de0c6735202acd575dbf32b310ec8ebad5 (diff) | |
| download | qemu-9e729b57ac2a3adebee2746a2106a70eb8230a72.zip | |
target-arm: A64: Refactor aarch64_cpu_do_interrupt
Introduce new_el and new_mode in preparation for future patches
that add support for taking exceptions to and from EL2 and 3.
No functional change.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1411718914-6608-4-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 8878d06904..a3ba624b74 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -500,6 +500,12 @@ void pmccntr_sync(CPUARMState *env); #define PSTATE_MODE_EL1t 4 #define PSTATE_MODE_EL0t 0 +/* Map EL and handler into a PSTATE_MODE. */ +static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) +{ + return (el << 2) | handler; +} + /* Return the current PSTATE value. For the moment we don't support 32<->64 bit * interprocessing, so we don't attempt to sync with the cpsr state used by * the 32 bit decoder. @@ -755,6 +761,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) } void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx); /* Interface between CPU and Interrupt controller. */ void armv7m_nvic_set_pending(void *opaque, int irq); |