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authorAurelio C. Remonda <aurelioremonda@gmail.com>2015-06-19 14:17:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-06-19 14:17:44 +0100
commitba890a9b2509a0087bb7eafddae02ea5ecbb7bb4 (patch)
tree908673b310fe8c474e08c9d4663044ff4df197af /target-arm/cpu.c
parentffdb1409a79c9cc91afd9f58df625fdca16bf8b9 (diff)
downloadqemu-ba890a9b2509a0087bb7eafddae02ea5ecbb7bb4.zip
target-arm: Add the Cortex-M4 CPU
This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3, the main differences being the DSP instructions and an optional FPU. Only no-FPU cortex-M4 is implemented here, cortex-M4F is not because the core target-arm code doesn't support the M-profile FPU model yet. Signed-off-by: Aurelio C. Remonda <aurelioremonda@gmail.com> Message-id: 1434461850-4104-1-git-send-email-aurelioremonda@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.c')
-rw-r--r--target-arm/cpu.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7496983b42..524e8414ad 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -812,6 +812,15 @@ static void cortex_m3_initfn(Object *obj)
cpu->midr = 0x410fc231;
}
+static void cortex_m4_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fc240; /* r0p0 */
+}
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
@@ -1214,6 +1223,8 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
.class_init = arm_v7m_class_init },
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
+ .class_init = arm_v7m_class_init },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },