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| author | Sergey Fedorov <serge.fdrv@gmail.com> | 2015-04-26 16:49:25 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-04-26 16:49:25 +0100 |
| commit | 7ebd5f2e03a00889619bb97e83062d27066d4a26 (patch) | |
| tree | 52580739f4c9e678966c0c96b3b5c68a38a2e57e /target-arm/cpu.c | |
| parent | ef7bab8d73580b48bda83b8d16b5eea8a3ac43fe (diff) | |
| download | qemu-7ebd5f2e03a00889619bb97e83062d27066d4a26.zip | |
target-arm: rename c1_coproc to cpacr_el1
Rename the field holding CPACR_EL1 system register state in AArch64
naming style.
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
[PMM: also fixed a couple of missed occurrences in cpu.c]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 986f04cfd6..3b5a93dbca 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -111,7 +111,7 @@ static void arm_cpu_reset(CPUState *s) /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; /* and to the FP/Neon instructions */ - env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); + env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -126,7 +126,7 @@ static void arm_cpu_reset(CPUState *s) } else { #if defined(CONFIG_USER_ONLY) /* Userspace expects access to cp10 and cp11 for FP/Neon */ - env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf); + env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); #endif } |