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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2013-02-25 11:41:38 -0800 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2013-02-25 14:32:36 -0600 |
| commit | 8c3ac601bdaf8d4d81823a79f2a166b586db7dab (patch) | |
| tree | 3ff6c46a76bdaa6c54010ffd2c42713e9519123f /target-arm/cpu-qom.h | |
| parent | a345481baa2b2fb3d54f8c9ddb58dfcaf75786df (diff) | |
| download | qemu-8c3ac601bdaf8d4d81823a79f2a166b586db7dab.zip | |
arm/translate.c: Fix adc_CC/sbc_CC implementation
commits 49b4c31efcce45ab714f286f14fa5d5173f9069d and
2de68a4900ef6eb67380b0c128abfe1976bc66e8 reworked the implementation of adc_CC
and sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path)
are incorrect. The new logic is:
CF:NF = 0:A +/- 0:CF
CF:NF = CF:A +/- 0:B
The lower 32 bits of the intermediate result stored in NF needs to be passes
into the second addition in place of A (s/CF:A/CF:NF):
CF:NF = 0:A +/- 0:CF
CF:NF = CF:NF +/- 0:B
This patch fixes the issue.
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'target-arm/cpu-qom.h')
0 files changed, 0 insertions, 0 deletions