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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-03-25 14:35:18 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2014-03-25 23:36:35 +0100 |
| commit | 7f6613cedc59fa849105668ae971dc31004bca1c (patch) | |
| tree | 5d9243d510446d94a22d10e44af7c29f38bb16c2 /linux-user | |
| parent | b9bf8a1abb1cafe7184e3dbad9bf8819b3cb620a (diff) | |
| download | qemu-7f6613cedc59fa849105668ae971dc31004bca1c.zip | |
target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode
Previous implementation presumed that FPU registers are 64-bit and are
working in 64-bit mode. This change first checks MIPS_HFLAG_F64 and if not
set, it does load/store from the odd numbered register pair.
Patch by Matthew Fortune.
Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com>
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'linux-user')
0 files changed, 0 insertions, 0 deletions