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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-16 12:14:00 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 13514fc93e6b2ead6e984bcd104975b6b4f375e8 (patch) | |
| tree | 0a1ea93a3afe95fdc91cdf4ae10ad69e5d3526f3 /linux-user | |
| parent | d913c3992dfd9506a8201c2995d7c910a18db92f (diff) | |
| download | qemu-13514fc93e6b2ead6e984bcd104975b6b4f375e8.zip | |
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
Diffstat (limited to 'linux-user')
| -rw-r--r-- | linux-user/mips/cpu_loop.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index f0831379cc..e400166c58 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,8 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) prog_req.fre &= interp_req.fre; bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS32R6 || - env->insn_flags & ISA_MIPS64R6; + env->insn_flags & ISA_MIPS32R6; if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |= (1 << CP0C5_FRE); |