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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-19 21:54:38 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:41:38 -0700 |
| commit | 5a8e01366c5dfe93f608e7d37f385962495d5161 (patch) | |
| tree | ca9cded97f936ff994bec3ee8bd21f86675805b6 /linux-user/microblaze | |
| parent | 78e9caf2f9410c8b90bb6d5a6449c750056c3f8a (diff) | |
| download | qemu-5a8e01366c5dfe93f608e7d37f385962495d5161.zip | |
target/microblaze: Split out FSR from env->sregs
Continue eliminating the sregs array in favor of individual members.
Does not correct the width of FSR, yet.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'linux-user/microblaze')
| -rw-r--r-- | linux-user/microblaze/cpu_loop.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index c10e3e0261..da5e98b784 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env) case ESR_EC_FPU: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; - if (env->sregs[SR_FSR] & FSR_IO) { + if (env->fsr & FSR_IO) { info.si_code = TARGET_FPE_FLTINV; } - if (env->sregs[SR_FSR] & FSR_DZ) { + if (env->fsr & FSR_DZ) { info.si_code = TARGET_FPE_FLTDIV; } info._sifields._sigfault._addr = 0; |