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| author | Tiejun Chen <tiejun.chen@intel.com> | 2015-07-15 13:37:47 +0800 |
|---|---|---|
| committer | Stefano Stabellini <stefano.stabellini@eu.citrix.com> | 2015-09-10 12:04:28 +0000 |
| commit | bd8107d7301d3fa44f04aa435e06efb2226ca58c (patch) | |
| tree | 8301bac0f5e9fc80e60778b0f421257625f966e6 /include | |
| parent | 881213f1b9c5a8f4101405a5802d548cb62a4274 (diff) | |
| download | qemu-bd8107d7301d3fa44f04aa435e06efb2226ca58c.zip | |
igd gfx passthrough: create a isa bridge
Currently IGD drivers always need to access PCH by 1f.0. But we
don't want to poke that directly to get ID, and although in real
world different GPU should have different PCH. But actually the
different PCH DIDs likely map to different PCH SKUs. We do the
same thing for the GPU. For PCH, the different SKUs are going to
be all the same silicon design and implementation, just different
features turn on and off with fuses. The SW interfaces should be
consistent across all SKUs in a given family (eg LPT). But just
same features may not be supported.
Most of these different PCH features probably don't matter to the
Gfx driver, but obviously any difference in display port connections
will so it should be fine with any PCH in case of passthrough.
So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell)
scenarios, 0x9cc3 for BDW(Broadwell).
Signed-off-by: Tiejun Chen <tiejun.chen@intel.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/i386/pc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 5cda2a3ff6..0639e46b2a 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -726,4 +726,5 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); (m)->compat_props = props; \ } while (0) +extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); #endif |