diff options
| author | Jason Wang <jasowang@redhat.com> | 2016-12-30 18:09:15 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2017-01-10 05:56:59 +0200 |
| commit | 615c4ed20598ab3eda5e071ba7ba2a5bf70be59f (patch) | |
| tree | 28db0d008fd713671715aba171b882c41fd1f60d /include | |
| parent | 554f5e16046236b264c66436870be1b4ef25c1dc (diff) | |
| download | qemu-615c4ed20598ab3eda5e071ba7ba2a5bf70be59f.zip | |
virtio-pci: address space translation service (ATS) support
This patches enable the Address Translation Service support for virtio
pci devices. This is needed for a guest visible Device IOTLB
implementation and will be required by vhost device IOTLB API
implementation for intel IOMMU.
Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/pci/pcie.h | 4 | ||||
| -rw-r--r-- | include/standard-headers/linux/pci_regs.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 056d25e53c..b08451d2c5 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -74,6 +74,9 @@ struct PCIExpressDevice { /* AER */ uint16_t aer_cap; PCIEAERLog aer_log; + + /* Offset of ATS capability in config space */ + uint16_t ats_cap; }; #define COMPAT_PROP_PCP "power_controller_present" @@ -120,6 +123,7 @@ void pcie_add_capability(PCIDevice *dev, void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num); +void pcie_ats_init(PCIDevice *dev, uint16_t offset); extern const VMStateDescription vmstate_pcie_device; diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h index e5a2e68b22..be5b066aa4 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -678,6 +678,7 @@ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM #define PCI_EXT_CAP_DSN_SIZEOF 12 +#define PCI_EXT_CAP_ATS_SIZEOF 8 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 /* Advanced Error Reporting */ |