diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2021-01-15 15:00:27 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-01-16 14:34:46 -0800 |
| commit | a8259b53230782f5e0a0d66013655c4ed5d71b7e (patch) | |
| tree | 682f8a500c9935c88f2f93ac6fd0cf44a7e4e0a1 /include/hw/riscv | |
| parent | 138ca49a82b978f035b709abee45324dd7ab3e68 (diff) | |
| download | qemu-a8259b53230782f5e0a0d66013655c4ed5d71b7e.zip | |
riscv: Pass RISCVHartArrayState by pointer
We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.
Fixes: Coverity CID 1438099
Fixes: Coverity CID 1438100
Fixes: Coverity CID 1438101
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/boot.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 20ff5fe5e5..11a21dd584 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -24,9 +24,9 @@ #include "hw/loader.h" #include "hw/riscv/riscv_hart.h" -bool riscv_is_32bit(RISCVHartArrayState harts); +bool riscv_is_32bit(RISCVHartArrayState *harts); -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts, +target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, target_ulong firmware_end_addr); target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, @@ -42,7 +42,7 @@ target_ulong riscv_load_kernel(const char *kernel_filename, hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); -void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts, +void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, |