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authorLeon Alrae <leon.alrae@imgtec.com>2016-03-15 09:59:26 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2016-03-30 09:13:58 +0100
commit8e7e8a5b7b95c143f396f6aadd310e9ff2f7efd3 (patch)
treea905d2e3e41417a9d5fce79f541096619d71c4ee /include/hw/mips
parent553934db664ecee676650fac0330dceff3531736 (diff)
downloadqemu-8e7e8a5b7b95c143f396f6aadd310e9ff2f7efd3.zip
hw/mips: implement generic MIPS Coherent Processing System container
Implement generic MIPS Coherent Processing System (CPS) which in this commit just creates VPs, but it will serve as a container also for other components like Global Configuration Registers and Cluster Power Controller. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'include/hw/mips')
-rw-r--r--include/hw/mips/cps.h40
1 files changed, 40 insertions, 0 deletions
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
new file mode 100644
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+++ b/include/hw/mips/cps.h
@@ -0,0 +1,40 @@
+/*
+ * Coherent Processing System emulation.
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MIPS_CPS_H
+#define MIPS_CPS_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_MIPS_CPS "mips-cps"
+#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
+
+typedef struct MIPSCPSState {
+ SysBusDevice parent_obj;
+
+ uint32_t num_vp;
+ uint32_t num_irq;
+ char *cpu_model;
+
+ MemoryRegion container;
+} MIPSCPSState;
+
+qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
+
+#endif