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| author | Cédric Le Goater <clg@kaod.org> | 2019-11-19 15:11:56 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-12-16 10:46:34 +0000 |
| commit | aab90b1cacb8b808d4f00c9709595c50b9d1f7a2 (patch) | |
| tree | 0f430c7d9e6afe9ef146ccd3662410d3a3943bb0 /include/hw/i2c/aspeed_i2c.h | |
| parent | 6054fc73e8f4acaafa63b4616e39414e53bce9a9 (diff) | |
| download | qemu-aab90b1cacb8b808d4f00c9709595c50b9d1f7a2.zip | |
aspeed/i2c: Check SRAM enablement on AST2500
The SRAM must be enabled before using the Buffer Pool mode or the DMA
mode. This is not required on other SoCs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-3-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/i2c/aspeed_i2c.h')
| -rw-r--r-- | include/hw/i2c/aspeed_i2c.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 5313d07aa7..7a555072df 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -61,6 +61,7 @@ typedef struct AspeedI2CState { qemu_irq irq; uint32_t intr_status; + uint32_t ctrl_global; MemoryRegion pool_iomem; uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; @@ -83,6 +84,8 @@ typedef struct AspeedI2CClass { uint64_t pool_size; hwaddr pool_base; uint8_t *(*bus_pool_base)(AspeedI2CBus *); + bool check_sram; + } AspeedI2CClass; I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr); |