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authorCédric Le Goater <clg@kaod.org>2019-09-25 16:32:41 +0200
committerPeter Maydell <peter.maydell@linaro.org>2019-10-15 18:09:04 +0100
commit51dd49236ba4bc20575b17abab26133957e38e91 (patch)
treed5aa61615c3d6009fef83db306c02bdb0ca76eaa /include/hw/i2c/aspeed_i2c.h
parentf7da1aa8fee9d0a4eb013ff8c173ead5a26e930e (diff)
downloadqemu-51dd49236ba4bc20575b17abab26133957e38e91.zip
aspeed/i2c: Add AST2600 support
The I2C controller of the AST2400 and AST2500 SoCs have one IRQ shared by all I2C busses. The AST2600 SoC I2C controller has one IRQ per bus and 16 busses. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-17-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/i2c/aspeed_i2c.h')
-rw-r--r--include/hw/i2c/aspeed_i2c.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index 6e2dae7db8..13e0105918 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -27,10 +27,11 @@
#define TYPE_ASPEED_I2C "aspeed.i2c"
#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
+#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
#define ASPEED_I2C(obj) \
OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C)
-#define ASPEED_I2C_NR_BUSSES 14
+#define ASPEED_I2C_NR_BUSSES 16
struct AspeedI2CState;
@@ -41,6 +42,7 @@ typedef struct AspeedI2CBus {
I2CBus *bus;
uint8_t id;
+ qemu_irq irq;
uint32_t ctrl;
uint32_t timing[2];
@@ -72,6 +74,7 @@ typedef struct AspeedI2CClass {
uint8_t num_busses;
uint8_t reg_size;
uint8_t gap;
+ qemu_irq (*bus_get_irq)(AspeedI2CBus *);
} AspeedI2CClass;
I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr);