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authorPeter Maydell <peter.maydell@linaro.org>2021-01-28 11:41:30 +0000
committerPeter Maydell <peter.maydell@linaro.org>2021-01-29 15:54:42 +0000
commit13059a3a101f9deb415100286e8b62cc2f4561a3 (patch)
treed15aa1edcebe1b525646f7af19d00095f249929d /include/hw/arm
parenteeae0b2bf4e69de27a133c87951ce52c6bfdb8b7 (diff)
downloadqemu-13059a3a101f9deb415100286e8b62cc2f4561a3.zip
hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"
While we transition the ARMSSE code from integer properties specifying clock frequencies to Clock objects, we want to have the device provide both at once. We want the final name of the main input Clock to be "MAINCLK", following the hardware name. Unfortunately creating an input Clock with a name X creates an under-the-hood QOM property X; for "MAINCLK" this clashes with the existing UINT32 property of that name. Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be deleted. Commit created with: perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210128114145.20536-11-peter.maydell@linaro.org Message-id: 20210121190622.22000-11-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/arm')
-rw-r--r--include/hw/arm/armsse.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 83f5e28c16..4860a793f4 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -39,7 +39,7 @@
* QEMU interface:
* + QOM property "memory" is a MemoryRegion containing the devices provided
* by the board model.
- * + QOM property "MAINCLK" is the frequency of the main system clock
+ * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
* (In hardware, the SSE-200 permits the number of expansion interrupts
* for the two CPUs to be configured separately, but we restrict it to