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| author | Niek Linnenbank <nieklinnenbank@gmail.com> | 2020-03-11 23:18:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-12 16:27:33 +0000 |
| commit | b71d0385e97e230b45a88c604756c44a748736fb (patch) | |
| tree | b616aa90b05ea1acb4e497fe6aa1d9cabe759864 /include/hw/arm/allwinner-h3.h | |
| parent | a80beb160d4e89937b0afccb146a9f3247f88588 (diff) | |
| download | qemu-b71d0385e97e230b45a88c604756c44a748736fb.zip | |
hw/arm/allwinner-h3: add SDRAM controller device
In the Allwinner H3 SoC the SDRAM controller is responsible
for interfacing with the external Synchronous Dynamic Random
Access Memory (SDRAM). Types of memory that the SDRAM controller
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
adds emulation support of the Allwinner H3 SDRAM controller.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/allwinner-h3.h')
| -rw-r--r-- | include/hw/arm/allwinner-h3.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index d338003724..065d020c73 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -41,6 +41,7 @@ #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-ccu.h" #include "hw/misc/allwinner-cpucfg.h" +#include "hw/misc/allwinner-h3-dramc.h" #include "hw/misc/allwinner-h3-sysctrl.h" #include "hw/misc/allwinner-sid.h" #include "hw/sd/allwinner-sdhost.h" @@ -80,6 +81,9 @@ enum { AW_H3_UART2, AW_H3_UART3, AW_H3_EMAC, + AW_H3_DRAMCOM, + AW_H3_DRAMCTL, + AW_H3_DRAMPHY, AW_H3_GIC_DIST, AW_H3_GIC_CPU, AW_H3_GIC_HYP, @@ -120,6 +124,7 @@ typedef struct AwH3State { AwA10PITState timer; AwH3ClockCtlState ccu; AwCpuCfgState cpucfg; + AwH3DramCtlState dramc; AwH3SysCtrlState sysctrl; AwSidState sid; AwSdHostState mmc0; |