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author | Richard Henderson <richard.henderson@linaro.org> | 2021-11-29 11:56:07 +0100 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2021-11-29 11:56:07 +0100 |
commit | e750c10167fa8ad3fcc98236a474c46e52e7c18c (patch) | |
tree | 12c2f042b62694d2ed39a2de28b9ea9256310e22 /include/exec | |
parent | dd4b0de45965538f19bb40c7ddaaba384a8c613a (diff) | |
parent | 90feffad2aafe856ed2af75313b2c1669ba671e9 (diff) | |
download | qemu-e750c10167fa8ad3fcc98236a474c46e52e7c18c.zip |
Merge tag 'pull-target-arm-20211129' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* virt: Diagnose attempts to enable MTE or virt when using HVF accelerator
* GICv3 ITS: Allow clearing of ITS CTLR Enabled bit
* GICv3: Update cached state after LPI state changes
* GICv3: Fix handling of LPIs in list registers
# gpg: Signature made Mon 29 Nov 2021 11:34:46 AM CET
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
* tag 'pull-target-arm-20211129' of https://git.linaro.org/people/pmaydell/qemu-arm:
hw/intc/arm_gicv3: fix handling of LPIs in list registers
hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function
hw/intc/arm_gicv3: Update cached state after LPI state changes
hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit
hw/arm/virt: Extend nested and mte checks to hvf
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/exec')
0 files changed, 0 insertions, 0 deletions