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| author | Emilio G. Cota <cota@braap.org> | 2017-07-06 14:42:26 -0400 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2017-10-10 07:37:10 -0700 |
| commit | 83974cf4f8a46513f799ff0d7c7eb151acafda7b (patch) | |
| tree | ce7c8add92d4cd60e832564b066be0c6a12c0e2b /include/exec/cputlb.h | |
| parent | 567d0a19c7998fa366598b83d5a6e5f0759d3ea9 (diff) | |
| download | qemu-83974cf4f8a46513f799ff0d7c7eb151acafda7b.zip | |
cputlb: bring back tlb_flush_count under !TLB_DEBUG
Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried
the increment of tlb_flush_count under TLB_DEBUG. This results in
"info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG.
Besides, under MTTCG tlb_flush_count is updated by several threads,
so in order not to lose counts we'd either have to use atomic ops
or distribute the counter, which is more scalable.
This patch does the latter by embedding tlb_flush_count in CPUArchState.
The global count is then easily obtained by iterating over the CPU list.
Note that this change also requires updating the accessors to
tlb_flush_count to use atomic_read/set whenever there may be conflicting
accesses (as defined in C11) to it.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/exec/cputlb.h')
| -rw-r--r-- | include/exec/cputlb.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f941783c5..c91db211bc 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,7 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -extern int tlb_flush_count; - +size_t tlb_flush_count(void); #endif #endif |