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| author | Scott Wood <scottwood@freescale.com> | 2013-01-21 15:53:54 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-01-25 22:02:56 +0100 |
| commit | bd25922e737a2c90668a7bdd1e1319413a7a51f3 (patch) | |
| tree | e751c36074af08723a99a190c9adcddd8ddee81a /hw | |
| parent | e0dfe5b18919a6a4deb841dcf3212e3e998c95e5 (diff) | |
| download | qemu-bd25922e737a2c90668a7bdd1e1319413a7a51f3.zip | |
PPC: e500: fix mpic_iack address
MPIC+0xa0 is IACK for the current CPU. MPIC+0x200a0 is IACK for CPU 0.
This fix allows EPR to work with an SMP target.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/ppc/e500.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 9ccf4d1840..530f9290f0 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -505,7 +505,7 @@ void ppce500_init(PPCE500Params *params) irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; env->mpic_iack = MPC8544_CCSRBAR_BASE + - MPC8544_MPIC_REGS_OFFSET + 0x200A0; + MPC8544_MPIC_REGS_OFFSET + 0xa0; ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); |