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author | Alistair Francis <alistair.francis@xilinx.com> | 2014-01-31 14:47:33 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-31 14:47:33 +0000 |
commit | b48adc0d301464d627d6d0f83dee911a2138187f (patch) | |
tree | 3476e13904b891d8dc8317d826cf7255b6390b6e /hw | |
parent | 51a9b04bd3b01e11a1db4fc2ac2f1d324fbd30aa (diff) | |
download | qemu-b48adc0d301464d627d6d0f83dee911a2138187f.zip |
ZYNQ: Implement board MIDR control for Zynq
This patch uses the fact that the midr variable is now a property
This patch sets the midr variable to the boards custom midr
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: a3754b10d150af72e4688a993e484fa2b9b8fa21.1390176489.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/arm/xilinx_zynq.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 98e0958a77..9ee21e726a 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -37,6 +37,7 @@ #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ #define MPCORE_PERIPHBASE 0xF8F00000 +#define ZYNQ_BOARD_MIDR 0x413FC090 static const int dma_irqs[8] = { 46, 47, 48, 49, 72, 73, 74, 75 @@ -125,6 +126,12 @@ static void zynq_init(QEMUMachineInitArgs *args) cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); + object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", &err); + if (err) { + error_report("%s", error_get_pretty(err)); + exit(1); + } + object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err); if (err) { error_report("%s", error_get_pretty(err)); |