diff options
| author | Joel Stanley <joel@jms.id.au> | 2018-08-16 14:05:29 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-16 14:29:58 +0100 |
| commit | b33f1e0b8921c95d744880e9f963b16a00653cad (patch) | |
| tree | 9956f930aa2fc6f745f19989c56e48f7590f373d /hw | |
| parent | d131bc28a6094191471fb935a0535ae5a4df4ab3 (diff) | |
| download | qemu-b33f1e0b8921c95d744880e9f963b16a00653cad.zip | |
aspeed_sdmc: Set 'cache initial sequence' always true
The SDRAM training routine sets the 'Enable cache initial' bit, and then
waits for the 'cache initial sequence' to be done.
Have it always return done, as there is no other side effects that the
model needs to implement. This allows the upstream u-boot training to
proceed on the ast2500-evb board.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180807075757.7242-4-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/misc/aspeed_sdmc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 24fd4aee2d..9ece545c4f 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -226,6 +226,7 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) s->ram_bits = ast2500_rambits(s); s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | + ASPEED_SDMC_CACHE_INITIAL_DONE | ASPEED_SDMC_DRAM_SIZE(s->ram_bits); break; default: |