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authorAndrew Jeffery <andrew@aj.id.au>2018-07-16 17:18:41 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-07-16 17:18:41 +0100
commit333b9c8a684c58f6711521e446e4b26de5addadc (patch)
tree58025693c3940e354eb86b3402c476422740f335 /hw
parent628fc75f3a3bb115de3b445c1a18547c44613cfe (diff)
downloadqemu-333b9c8a684c58f6711521e446e4b26de5addadc.zip
aspeed: Implement write-1-{set, clear} for AST2500 strapping
The AST2500 SoC family changes the runtime behaviour of the hardware strapping register (SCU70) to write-1-set/write-1-clear, with write-1-clear implemented on the "read-only" SoC revision register (SCU7C). For the the AST2400, the hardware strapping is runtime-configured with read-modify-write semantics. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20180709143524.17480-1-andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/misc/aspeed_scu.c19
1 files changed, 17 insertions, 2 deletions
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 59333b50ab..c8217740ef 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -247,11 +247,26 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
s->regs[reg] = data;
aspeed_scu_set_apb_freq(s);
break;
-
+ case HW_STRAP1:
+ if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
+ s->regs[HW_STRAP1] |= data;
+ return;
+ }
+ /* Jump to assignment below */
+ break;
+ case SILICON_REV:
+ if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
+ s->regs[HW_STRAP1] &= ~data;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ }
+ /* Avoid assignment below, we've handled everything */
+ return;
case FREQ_CNTR_EVAL:
case VGA_SCRATCH1 ... VGA_SCRATCH8:
case RNG_DATA:
- case SILICON_REV:
case FREE_CNTR4:
case FREE_CNTR4_EXT:
qemu_log_mask(LOG_GUEST_ERROR,