summaryrefslogtreecommitdiff
path: root/hw/sparc64
diff options
context:
space:
mode:
authorMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2017-12-21 07:32:57 +0000
committerMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2018-01-09 21:31:31 +0000
commit2a4d6af51b8330bfd7a7dd677927b8dd2f5f5f08 (patch)
tree44e3915a4ff2705b9ae35cd7c08680359f02ef2c /hw/sparc64
parent588978c0a1e9f5596a12d124b530bdf698ed9104 (diff)
downloadqemu-2a4d6af51b8330bfd7a7dd677927b8dd2f5f5f08.zip
apb: use gpios to wire up the apb device to the SPARC CPU IRQs
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>
Diffstat (limited to 'hw/sparc64')
-rw-r--r--hw/sparc64/sparc64.c2
-rw-r--r--hw/sparc64/sun4u.c12
2 files changed, 10 insertions, 4 deletions
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index 9453e2c390..95a06f00b2 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -350,6 +350,8 @@ SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr)
uint32_t hstick_frequency = 100 * 1000000;
cpu = SPARC_CPU(cpu_create(cpu_type));
+ qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq,
+ "ivec-irq", IVEC_MAX);
env = &cpu->env;
env->tick = cpu_timer_create("tick", cpu, tick_irq,
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index a64ddc569d..2afd3f28dd 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -486,7 +486,6 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
PCIBus *pci_bus, *pci_busA, *pci_busB;
PCIDevice *ebus, *pci_dev;
SysBusDevice *s;
- qemu_irq *ivec_irqs;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DeviceState *dev;
FWCfgState *fw_cfg;
@@ -502,9 +501,14 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
prom_init(hwdef->prom_addr, bios_name);
- ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX);
- apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA,
- &pci_busB);
+ apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, &pci_busA, &pci_busB);
+
+ /* Wire up PCI interrupts to CPU */
+ for (i = 0; i < IVEC_MAX; i++) {
+ qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i,
+ qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
+ }
+
pci_bus = PCI_HOST_BRIDGE(apb)->bus;
/* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is